library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.dec_pkg.all;


entity p_conv is
port(
		clk,reset: in std_ulogic;
		q1,q2,q3,q4,q5,q6,q7,q8: in std_ulogic_vector(15 downto 0);
		l_w1,l_w2,l_w3,l_w4,l_w5,l_w6,l_w7,l_w8:out matrix_23_20
		);
end p_conv;

architecture beh of p_conv is

signal p1,p2,p3,p4,p5,p6,p7,p8:std_ulogic_vector(15 downto 0);
signal v_w1,v_w2,v_w3,v_w4,v_w5,v_w6,v_w7,v_w8:std_ulogic_vector(15 downto 0); 
signal v1_w1,v1_w2,v1_w3,v1_w4,v1_w5,v1_w6,v1_w7,v1_w8:std_ulogic_vector(15 downto 0); 
signal v2_w1,v2_w2,v2_w3,v2_w4,v2_w5,v2_w6,v2_w7,v2_w8:std_ulogic_vector(15 downto 0); 


component denominator     ---Denominator
port(
    clk: in std_ulogic;
	 q1,q2,q3,q4,q5,q6,q7,q8: in std_ulogic_vector(15 downto 0);
	 vtmp_w1,vtmp_w2,vtmp_w3,vtmp_w4,vtmp_w5,vtmp_w6,vtmp_w7,vtmp_w8: out std_ulogic_vector(15 downto 0)
	 );
end component;


component numerator_w1  -----------Numerator
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;

component numerator_w2
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w3
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w4
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w5
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w6
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w7
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;
--
component numerator_w8
port(
      clk,reset: in std_ulogic;
		q_1,q_2,q_3,q_4,q_5,q_6,q_7: in std_ulogic_vector(15 downto 0);
		vtmp: in std_ulogic_vector(15 downto 0);
		p_wire_w:out matrix_23_20
	);
end component;


begin

--process(clk)
--  begin
--    if clk'event and clk='1'  then
--    p1<=q1;
--    p2<=q2;
--    p3<=q3;
--    p4<=q4;
--    p5<=q5;
--    p6<=q6;
--    p7<=q7;
--    p8<=q8;
-- end if;
--  end process;
  
  process(clk)
    begin
      if clk'event and clk='1'  then
        v1_w1<=v_w1;
        v1_w2<=v_w2;
        v1_w3<=v_w3;
        v1_w4<=v_w4;
        v1_w5<=v_w5;
        v1_w6<=v_w6;
        v1_w7<=v_w7;
        v1_w8<=v_w8;
      end if;
    end process;
    
    --process(clk)
--    begin
--      if clk'event and clk='1'  then
--        v2_w1<=v1_w1;
--        v2_w2<=v1_w2;
--        v2_w3<=v1_w3;
--        v2_w4<=v1_w4;
--        v2_w5<=v1_w5;
--        v2_w6<=v1_w6;
--        v2_w7<=v1_w7;
--        v2_w8<=v1_w8;
--      end if;
--    end process;

--c1:denominator  port map(clk=>clk,q1=>p1,q2=>p2,q3=>p3,q4=>p4,q5=>p5,q6=>p6,q7=>p7,q8=>p8,vtmp_w1=>v_w1,vtmp_w2=>v_w2,vtmp_w3=>v_w3,vtmp_w4=>v_w4,vtmp_w5=>v_w5,vtmp_w6=>v_w6,vtmp_w7=>v_w7,vtmp_w8=>v_w8);
--c2:numerator_w1 port map(clk=>clk,reset=>reset,q_1=>p2,q_2=>p3,q_3=>p4,q_4=>p5,q_5=>p6,q_6=>p7,q_7=>p8,vtmp=>v1_w1,p_wire_w(0 to 22)=>l_w1(0 to 22));
--c3:numerator_w2 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p3,q_3=>p4,q_4=>p5,q_5=>p6,q_6=>p7,q_7=>p8,vtmp=>v1_w2,p_wire_w(0 to 22)=>l_w2(0 to 22));
--c4:numerator_w3 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p4,q_4=>p5,q_5=>p6,q_6=>p7,q_7=>p8,vtmp=>v1_w3,p_wire_w(0 to 22)=>l_w3(0 to 22));
--c5:numerator_w4 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p3,q_4=>p5,q_5=>p6,q_6=>p7,q_7=>p8,vtmp=>v1_w4,p_wire_w(0 to 22)=>l_w4(0 to 22));
--c6:numerator_w5 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p3,q_4=>p4,q_5=>p6,q_6=>p7,q_7=>p8,vtmp=>v1_w5,p_wire_w(0 to 22)=>l_w5(0 to 22));
--c7:numerator_w6 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p3,q_4=>p4,q_5=>p5,q_6=>p7,q_7=>p8,vtmp=>v1_w6,p_wire_w(0 to 22)=>l_w6(0 to 22));
--c8:numerator_w7 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p3,q_4=>p4,q_5=>p5,q_6=>p6,q_7=>p8,vtmp=>v1_w7,p_wire_w(0 to 22)=>l_w7(0 to 22));
--c9:numerator_w8 port map(clk=>clk,reset=>reset,q_1=>p1,q_2=>p2,q_3=>p3,q_4=>p4,q_5=>p5,q_6=>p6,q_7=>p7,vtmp=>v1_w8,p_wire_w(0 to 22)=>l_w8(0 to 22));

c1:denominator  port map(clk=>clk,q1=>q1,q2=>q2,q3=>q3,q4=>q4,q5=>q5,q6=>q6,q7=>q7,q8=>q8,vtmp_w1=>v_w1,vtmp_w2=>v_w2,vtmp_w3=>v_w3,vtmp_w4=>v_w4,vtmp_w5=>v_w5,vtmp_w6=>v_w6,vtmp_w7=>v_w7,vtmp_w8=>v_w8);
c2:numerator_w1 port map(clk=>clk,reset=>reset,q_1=>q2,q_2=>q3,q_3=>q4,q_4=>q5,q_5=>q6,q_6=>q7,q_7=>q8,vtmp=>v1_w1,p_wire_w(0 to 22)=>l_w1(0 to 22));
c3:numerator_w2 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q3,q_3=>q4,q_4=>q5,q_5=>q6,q_6=>q7,q_7=>q8,vtmp=>v1_w2,p_wire_w(0 to 22)=>l_w2(0 to 22));
c4:numerator_w3 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q4,q_4=>q5,q_5=>q6,q_6=>q7,q_7=>q8,vtmp=>v1_w3,p_wire_w(0 to 22)=>l_w3(0 to 22));
c5:numerator_w4 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q3,q_4=>q5,q_5=>q6,q_6=>q7,q_7=>q8,vtmp=>v1_w4,p_wire_w(0 to 22)=>l_w4(0 to 22));
c6:numerator_w5 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q3,q_4=>q4,q_5=>q6,q_6=>q7,q_7=>q8,vtmp=>v1_w5,p_wire_w(0 to 22)=>l_w5(0 to 22));
c7:numerator_w6 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q3,q_4=>q4,q_5=>q5,q_6=>q7,q_7=>q8,vtmp=>v1_w6,p_wire_w(0 to 22)=>l_w6(0 to 22));
c8:numerator_w7 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q3,q_4=>q4,q_5=>q5,q_6=>q6,q_7=>q8,vtmp=>v1_w7,p_wire_w(0 to 22)=>l_w7(0 to 22));
c9:numerator_w8 port map(clk=>clk,reset=>reset,q_1=>q1,q_2=>q2,q_3=>q3,q_4=>q4,q_5=>q5,q_6=>q6,q_7=>q7,vtmp=>v1_w8,p_wire_w(0 to 22)=>l_w8(0 to 22));



end beh;
